The present invention relates to design technology for integrated circuit devices such as system LSI, and more particularly, relates to smoothing designing in a sequence of design process steps up to register-transfer level (RTL) design process step.
In general, design of an integrated circuit device is performed in a procedure as shown in FIG. 42, where specification/behavioral level design (S91) comes first followed by RTL design (S92), gate level design (S93), and mask level design (S94) in this order.
In the specification/behavioral level design, specifications and behavior for implementing a certain function are designed. In the RTL design, data throughput and the time required for processing data, as well as hardware configuration and the area occupied by the hardware, are taken into consideration.
The subsequent designs lower in level than the RTL design have been automated, and therefore design data can be generated without the necessity of manual work.
On the contrary, the upper-level designs including the RTL design have been little automated. Design and optimization are performed by skilled designers. Local optimization is therefore difficult due to restriction on the number of steps and the like, and thus only broad-perspective optimization has been made. If local optimization can be done in the upper-level designs, a great effect may possibly be exerted on the entire design. In consideration of this, a simple and convenient optimization design method has been desired.
Conventionally, there has been established no standard information style exchangeable between the specification/behavioral level design and the RTL design. Accordingly, it is impossible to correctly grasp information on the RTL design at the stage of the specification/behavioral level design. For this reason, even a skilled designer tends to prepare, at the stage of the specification/behavioral level design, a design unable to be implemented in the RTL design. As a result, it may become necessary to correct the specification/behavioral level design after completion of the RTL design. Otherwise, a redundant circuit may be designed at the specification/behavioral level.
An object of the present invention is providing a method and an apparatus for designing an integrated circuit device, capable of designing a large-scale system such as system LCI efficiently by use of common information of the number of operations that is shared in the specification/behavioral level design process step and the RTL design process step, and capable of performing simple and convenient optimization design in these design process steps.
The first method for designing an integrated circuit device of the present invention is a method including representing a portion constituting the integrated circuit device by a three-dimensional shape, the type of the three-dimensional shape being determined depending on a design level.
By the above method, the structure of an element or a bus that is sequentially concretized in the course of specification levelxe2x80x94behavioral levelxe2x80x94RTL can be represented by three-dimensional shapes that allow for prompt grasp of the structure. This contributes to improvement in design efficiency. More specifically, since it is possible to roughly grasp the structure of an element or a bus in high-level design that is required for design of an integrated circuit device, the structure of a design model can be easily limited to an appropriate range. This reduces the possibility of such an occurrence that high-level design must be done again as a result of low-level design.
When the integrated circuit device has a plurality of functions, the above portion comprises a plurality of elements required for implementing the plurality of functions, and each of the plurality of elements may be represented by a three-dimensional shape of which a volume corresponds to the number of operations required for implementing the function.
In design at a level lower than a specification level, the element may be represented by a pole of which a bottom area corresponds to the number of operations per cycle.
In behavioral level design, the element may be represented by a cylinder of which a bottom is a circle having an area corresponding to the number of operations per cycle.
In RTL design, the element may be represented by a square pole of which a bottom has two adjacent sides corresponding to the number of operations per unit time and the period of a cycle.
When the portion comprises a bus connecting the plurality of elements, a connection relationship between the bus and each of the elements may be represented by a three-dimensional shape so that a structure of the bus and a structure of the element match each other using the number of operations per unit time as a medium.
In design at a level lower than a specification level, the element may be represented by a pole of which a bottom area corresponds to the number of operations per cycle, and the bus may be represented by a pole of which a bottom area corresponds to the number of operations per cycle.
Preferably, in behavioral level design, the element is represented by a cylinder of which a bottom is a circle having an area corresponding to the number of operations per cycle, and the bus is represented by a cylinder of which a bottom is a circle having an area corresponding to the number of operations per cycle.
Preferably, in RTL design, the element is represented by a square pole of which a bottom has two adjacent sides corresponding to the number of operations per unit time and a period of a cycle, and the bus is represented by a square pole of which a bottom has two adjacent sides corresponding to the number of operations per unit time and a period of a cycle.
When the bottom areas of the bus and the element are different from each other, the bus may be represented by a cone of which two faces correspond to the bottoms of the bus and the element.
A bus branch branching from the bus to be connected to the element may further be generated, the bus branch being represented by a pole having a cross-sectional area equal to the bottom area of the bus.
The second method for designing an integrated circuit device of the present invention includes the steps of: (a) obtaining the number of operations by simulating a function of the integrated circuit device; (b) determining specification level elements so that each of the elements has the number of operations equal to or more than the number of operations obtained in the step (a); (c) determining a bus connecting the elements; (d) determining behavioral level elements so that each of the elements has the number of operations per cycle and the number of cycles that give the number of operations equal to or more than the number of operations determined in the step (b); and (e) determining a behavioral level bus for connecting the behavioral level elements based on the number of operations per cycle determined in the step (d).
By the above method, consistent design based on the number of operations of an element and a bus is possible through the respective design stages.
In the step (b), if a plurality of practicable specification level elements exist, one among the elements that has the least number of operations may be determined as the specification level element used for design. With this determination, a circuit small in circuit area and power consumption can be obtained.
In the step (d), in the case where a plurality of practicable behavioral level elements exist, if design is made giving higher priority to operation speed, an element among the behavioral level elements that has the number of operations per cycle as large as possible may be determined as the behavioral level elements used for design, or if design is made giving higher priority to a smaller circuit area or smaller power consumption, an element among the behavioral level elements that has the number of operations per cycle as small as possible may be determined as the behavioral level element used for design. With this determination, it is possible to consider an item of high priority on design in the RTL design.
The integrated circuit device may further include the step of (f) obtaining design data corresponding to the behavioral level element for implementing the function.
In the step (d), a plurality of elements having the same function are preferably unified into a shared element.
In the step (d), in the unification, further preferably, an element among the plurality of elements that has the maximum number of operations per cycle is determined as the shared element.
Preferably, in the step (d), when an element is replaced with the shared element, a portion of the number of operations per cycle of the shared element exceeding the number of operations per cycle of the element to be replaced is not used. This reduces power consumption.
The method may further include the steps of: (g) determining a RTL element so as to have the number of operations per unit time and the period that give the number of operations per cycle equal to or more than the number of operations per cycle of the behavioral level element determined in the step (d); (h) determining a RTL bus based on the number of operations per unit time and the period; and (i) determining design data corresponding to the RTL element for implementing the function. This allows for consistent design of an element and a bus from the specification level through the RTL.
Preferably, in the step (g), in the case where a plurality of RTL practicable elements exist, if design is made giving higher priority to operation speed, an element among the RTL elements that has the number of operations per unit time as large as possible is selected, or if design is made giving higher priority to a smaller circuit area or smaller power consumption, an element among the RTL elements that has the number of operations per unit time as small as possible is selected. With this determination, it is possible to consider an item of high priority on design in the RTL design.
In the step (d), for one specification level element, a plurality of behavioral level elements operating in parallel that have the total number of operations equal to the number of operations of the specification level element may be obtained. This provides flexibility for the layout of a circuit.
The integrated circuit device may execute a plurality of processes in parallel, and in the step (d), if there are behavioral level elements having the same type of function that can be shared among the plurality of processes, the behavioral level elements may be deformed so as to be executed at different times in the respective processes. With this deformation, design allowing for sharing of some circuits and the like is possible in the behavioral level design.
In the step (d), if the time period from completion of operation of a first behavioral level element until start of operation of a second behavioral level element is equal to or more than one cycle, the first behavioral level element may be deformed so that the number of operations per cycle is smaller, to thereby reduce the time period to less than one cycle. Thus, design can be done so that no data retaining circuit is necessary.
In the step (d), if the time period from completion of operation of a first behavioral level element until start of operation of a second behavioral level element is equal to or more than one cycle, a behavioral level element for a circuit that retains output data of the first behavioral level element for the time period may be obtained. In this case, a data retaining circuit of a necessary and sufficient scale is obtained.
In the step (g), RTL elements operating in parallel may be obtained for one behavioral level element. In this case, a RTL model with reduced power consumption is obtained.
In the step (g), RTL elements pipeline-operating sequentially may be obtained for one behavioral level element. In this case, a RTL model with a reduced circuit area is obtained.
In the step (b), processing may be paralleled for reducing the number of cycles required for the processing, and in the step (d), the behavioral level elements operating in parallel may be deformed so that the number of operations per cycle is smaller. This makes it possible to suppress the peak of power consumption without increasing the number of cycles.
In the step (b), each of the specification level elements may be represented by a three-dimensional shape having a volume corresponding to the number of operations of the element. In the step (d), each of the behavioral level elements may be represented by a pole having a cross-sectional area corresponding to the number of operations per cycle of the element and an axial length corresponding to the number of cycles of the element, and in the step (e), the behavioral level bus may be represented by a pole having a cross-sectional area corresponding to the number of operations per cycle of the bus. This makes the design efficient.
In the step (g), each of the RTL elements may be represented by a rectangle pole having a rectangular cross section of which two sides correspond to the number of operations and the period and an axial length corresponding to the number of cycles, and in the step (h), the RTL bus may be represented by a rectangle pole having a rectangular cross section of which two sides correspond to the number of operations and the period. This makes the design further efficient.
The elements may be retrieved from a database storing elements as design data.
The elements may be generated by a generator. This eliminates the necessity of preparing many behavioral models in a database since only a necessary behavioral model needs to be generated.
The design data may be that obtained by use of an IP described to generate: a circuit basic portion; parallel-connected circuit additional portions of the number corresponding to the value of an input parameter; and an adjusting circuit in relation to data input or output of the circuit additional portions. This makes it possible to generate circuits based on one IP, where part of the IP has a scale depending on the parameter.
The circuit basic portion may include: an operator circuit for performing an operation for input data and outputting operation results as well as an address signal designating a destination of the operation results and a data read/write control signal. Each of the circuit additional portions includes a buffer circuit for temporarily storing and then outputting the operation results in accordance with the address signal. The adjusting circuit includes a selection circuit for receiving outputs from the buffer circuits and the data read/write control signal, selecting one of the outputs from the buffer circuits in accordance with the data read/write control signal, and outputting the selected one. This also provides the above effect.
The database of the present invention is a database used for design of an integrated circuit device having a plurality of functions. The database includes: a design model section including specification level elements each having as a design parameter the number of operations required for implementing the plurality of functions, and behavioral level elements each having as design parameters the number of operations per cycle and the number of cycles; and a computation section including a relational expression for calculating the design parameters along the design models.
Having the above database, consistent design can be made for elements for implementing functions required for the integrated circuit device, using the number of operations as a common parameter for the specification level through the behavioral level.
The design model section may further include RTL elements each determined by the number of operations per unit time, the period, and the number of cycles, and the computation section may further include a relational expression for calculating the number of operations per unit time, the period, and the number of cycles from the number of operations and the number of cycles of the behavioral level element. This allows for consistent design extended to the RTL design.